![]() ![]() ![]() To run the simulation, you will have to open the design in the VHDL simulator that you are using with Quartus, for example ModelSim. The testbench can only be run in a VHDL simulator. It’s only the Timer module that’s synthesizable, not the testbench. You are probably trying to synthesize the testbench. Hi i tried to compiled by using quartus but i had a problem in this codeĮrror (10398): VHDL Process Statement error at T18_TimerTb.vhd(40): Process Statement must contain only one Wait Statement SetTimeout(function(), 1000) ġ9 thoughts on “How to create a timer in VHDL” Ĭorrect the error in the code: 100e6 - 100 MHz Notify me of replies to my comment via email Your email address will not be published.
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